Erasable-programmable read-only memories (EPROMs) are non-volatile semiconductor memory devices based on metal oxide semiconductor field effect transistors (MOSFETs). EPROM cells store a bit of information as a quantity of electrons on a floating gate structure insulatively formed between the channel and the control gate of the field effect transistor. A charged floating gate raises the threshold voltage of the field effect transistor channel above the voltage normally applied to the control gate during the read operation, thereby storing a logic "0". An uncharged floating gate does not alter the threshold voltage of the channel of the field effect transistor, and therefore a normal data reading voltage will exceed the threshold voltage thereby storing a logic "1".
One structure used in semiconductor memories is an array of EPROM cells supported in a package having a window for ultraviolet erasing. Typically these EPROM cells are fabricated in a structure often referred to in the art as the floating gate avalanche injection metal oxide semiconductor (FAMOS) structure. In this structure, the floating gate is charged by the transport of electrons from the drain of the field effect transistor by avalanche injection or by channel hot electron injection. An applied high voltage pulse to the control gate induces a conductive inversion layer from source to drain. If, for example, the source is grounded and the drain is pulsed with sufficient voltage, electrons will accelerate through the inversion area in the channel from the source to the drain. A number of these electrons will gain energy from the channel electric field and create additional electron hole-pairs. Some of the electrons created during this process ("hot" electrons) have a sufficient energy level to jump over potential barrier created by the insulator between the floating gate and the channel. A percentage of these "hot" electrons will in turn be drawn to the floating gate because of the voltage induced on the floating gate due to capacitive coupling with the control gate. These electrons come to reside on the floating gate thereby charging it. Subsequently the programmed cells (et to a logic "0") in the array may be erased or returned to the logic "1" state by having their respective floating gates discharged in bulk by exposure to ultraviolet light. Ultraviolet light is directed through the window in the package such that the surface across which the memory cells are formed is exposed to the ultraviolet radiation. A portion of this ultraviolet radiation reaches the electrons on the floating gates of the charged cells. The ultraviolet radiation increases the energy of these electrons such that they exceed the potential barrier of the gate oxide separating the floating gate from the channel. After sufficient exposure, substantially all of the electrons will jump the barrier of the gate oxide and return to the substrate such that the cells are erased.
Ultraviolet erasing has a significant disadvantage in that all of the EPROM cells in the array are erased in bulk. Many times, however, it is desirable to have certain ones of the cells in the array programmed once and then left in that state despite the programming, erasing, and reprogramming of the remaining cells in the array. For example, it may be desirable to permanently set certain cells to a specific state to account for defective cells in the array or for use in associated "fixed" circuitry. One method of providing such "permanently programmed" cells is through the use of the unerasable programmable read-only memory (UPROM) cells. Currently available UPROM cells are typically conventional EPROM cells having a shield disposed between themselves and the erasing window such that during the erasing operation for the EPROM array, no ultraviolet light can reach floating gates and discharge them.
Currently available UPROM cells have the first significant disadvantage of increased size over conventional EPROM cells. In order to sufficiently protect against exposure to ultraviolet light during the erasing of the associated array, the shield must be significantly large. The shield not only must protect the floating gates from ultraviolet light directed toward the cells at a substantially perpendicular angle, but the shield must also be large enough such that ultraviolet radiation either directed toward the cell at non-perpendicular angles or reflecting off other structures on the chip will not leak in around the edges of the shield. The use of large shields in turn makes the overall size of the memory cells substantially larger than that of conventional EPROM cells substantially reducing packing density on the array. Currently available UPROM cells are also subject a second substantial disadvantage; because of the need to access the source/drain and gate of the EPROM cell, currently available UPROM cells include openings in the shield which may allow ultraviolet light to penetrate into the cell area.
Thus, the need has arisen for a UPROM cell with reduced size which also provides sufficient protection from the penetration of ultraviolet light into the cell area during an erase operation. Further, such a cell would minimize the possibility of light reaching the floating gate through openings required to access the source/drain and control gate of the memory cell. Further, the need has arisen for a UPROM cell which can be fabricated concurrently with conventional EPROM cells.